Overview and History
Origins and Development
The VAX architecture was conceived at Digital Equipment Corporation (DEC) in the mid-1970s as a response to the limitations of the 16-bit PDP-11. DEC engineers, led by Gordon Bell, sought to create a 32-bit design that preserved the PDP-11’s software compatibility while vastly increasing addressable memory. Development began in 1975, and the first VAX system, the VAX-11/780, was announced in October 1977. The architecture introduced a flat 32-bit virtual address space, a rich orthogonal instruction set, and hardware support for virtual memory—features that were advanced for its time.
Market Position and Legacy
Throughout the 1980s, the VAX family dominated the mid-range minicomputer market. It was particularly popular in scientific research, engineering simulation, manufacturing, and commercial data processing. DEC’s VMS operating system, combined with the VAX’s reliability and scalability, made it a preferred platform for large-scale computing in universities, laboratories, and corporate data centers. By the late 1980s, VAX systems were deployed in thousands of installations worldwide, and the architecture was widely regarded as the pinnacle of CISC design.
Decline and Phase-out
The rise of RISC architectures and commodity microprocessors in the 1990s eroded the VAX’s market position. DEC attempted to transition to its own RISC architecture, Alpha, beginning in 1992, but the shift cannibalized VAX sales. The final VAX model, the VAX 7000/10000 series, was discontinued in 2000, and DEC itself was acquired by Compaq in 1998. Many VAX systems remained in service into the early 2000s, particularly in legacy industrial and military applications, before being replaced by more modern platforms.
Architecture
CPU Design and Instruction Set
The VAX CPU is a classic CISC (Complex Instruction Set Computer) design. Its instruction set includes over 300 operation codes, supporting operations on integers, floating-point numbers, character strings, and packed decimal data. The CPU employs microcoded control logic, with most instructions executing in multiple microcycles.
Orthogonal Addressing Modes
The VAX instruction set is highly orthogonal: any arithmetic or data movement instruction can use any addressing mode for any operand. Addressing modes include register direct, register deferred, immediate, absolute, indexed, autoincrement, autodecrement, and various combinations. This flexibility simplified compiler code generation but increased instruction complexity.
Variable-Length Instructions
VAX instructions are variable-length, ranging from one byte (e.g., NOP) to over 50 bytes for complex operations with many operands and addressing modes. The opcode byte determines the number and types of operands. The CPU decodes instructions sequentially, fetching operand specifiers as needed. This design contributed to dense code but also to variable execution times.
Memory Management
The VAX provides hardware-based virtual memory management. Each process sees a 32-bit virtual address space of up to 4 GB, divided into four regions: P0 (program space), P1 (control space), S0 (system space), and S1 (reserved). Address translation is done via a two-level page table hierarchy.
Virtual Address Space Layout
The virtual address is split into a 10-bit region field, a 21-bit virtual page number, and a 9-bit byte offset within the page (page size of 512 bytes in early models, later 1024 bytes). The region field selects one of four system page tables.
Page Tables and Translation Lookaside Buffer
Page tables are stored in memory and are indexed by the virtual page number. The Translation Lookaside Buffer (TLB) caches recently used page table entries to speed up address translation. The VAX TLB typically holds 128 entries and is fully associative. On a TLB miss, the CPU performs a multi-level page walk, which was a relatively slow operation.
Input/Output System
The VAX architecture decoupled I/O from CPU memory using dedicated I/O buses. Early models integrated the Unibus and Q-bus for connecting peripherals.
Unibus and Q-bus Integration
The Unibus was a high-speed 16-bit bus inherited from the PDP-11, supporting up to 21 devices. The Q-bus was a lower-cost variant, primarily used in MicroVAX systems. Both buses allowed direct memory access (DMA) and programmed I/O.
Massbus and Other I/O Channels
For high-performance disk and tape storage, the VAX used the Massbus interconnect, which supported higher transfer rates and larger block sizes. Later models added proprietary I/O channels, such as the VAX BI (Backplane Interconnect) and VAXCI (Computer Interconnect), enabling clustering and high-speed data paths.
Hardware Models
Early VAX Systems
The initial VAX systems were large, cabinet-based computers targeted at departmental and enterprise computing.
VAX-11/780
The VAX-11/780 was the first implementation, introduced in 1977. It used a bit-slice processor built from AMD 2901 chips, with a clock of 5 MHz and performance around 1 MIPS. It featured 128 KB to 8 MB of main memory and the Unibus for I/O. It became the reference model for VAX performance.
VAX-11/750 and VAX-11/730
The VAX-11/750 (1979) was a lower-cost, slower version (~0.6 MIPS) using a simpler microcode. The VAX-11/730 (1981) was further reduced in cost, offering about 0.3 MIPS. Both maintained software compatibility.
Mid-Range and High-End Models
As VLSI technology improved, DEC introduced more powerful, compact systems.
VAX 8600 Series
The VAX 8600 (1984) was a high-end model using a custom gate-array processor, achieving up to 4 MIPS. It supported larger memory (up to 68 MB) and introduced the VAXBI bus.
VAX 9000 Series
The VAX 9000 (1989) was the most powerful VAX, a mainframe-class system with multiple CPUs (up to 64 in some configurations) and performance exceeding 30 MIPS. It used ECL logic and water cooling, and it was the final high-end VAX model.
MicroVAX and Workstations
The MicroVAX line brought the VAX architecture to desktop and departmental systems.
MicroVAX II and III
The MicroVAX II (1984) used a single-chip microVAX processor and the Q-bus. It offered about 0.9 MIPS and was popular as a server. The MicroVAX III (1988) increased performance to 2.7 MIPS by using the CVAX chip.
VAXstation Families
VAXstation systems were targeted at graphics workstations. The VAXstation II/GPX (1985) included a monochrome display. The VAXstation 3100 and 4000 series (late 1980s–1990s) used faster processors and provided color graphics, often running Ultrix or VMS with a graphical user interface.
Software Ecosystem
VMS Operating System
VMS (Virtual Memory System) was the primary operating system for VAX, later renamed OpenVMS. It was designed specifically for the VAX architecture, offering process management, virtual memory, file system, and networking.
File System and Record Management
VMS used the Files-11 (ODS-2) file system, supporting hierarchical directories, file protection, and record-oriented I/O. Record Management Services (RMS) provided a standard interface for handling fixed-length, variable-length, and indexed file structures.
Clustering and Networking
VAXclusters, introduced in the 1980s, allowed multiple VAX systems to share storage and process workloads as a single system. DECnet was the primary networking protocol, supporting both local and wide-area communication.
Unix on VAX: Ultrix and Other Variants
DEC ported Unix to the VAX under the name Ultrix, first released in 1984. Ultrix offered a BSD-based environment and was popular in academic and research settings. Other Unix variants, such as 4.3BSD and System V, were also available from third parties.
Programming Languages and Tools
The VAX ecosystem provided a rich set of software development tools.
Compilers for Fortran, C, and COBOL
DEC supplied high-quality compilers for Fortran, C, COBOL, Pascal, and PL/I, all tightly integrated with VMS and Ultrix. The VAX FORTRAN compiler, in particular, was widely used in scientific computing.
Debuggers and Performance Analyzers
The VMS Debugger (set breakpoints, trace, examine memory) was a command-line tool. The VAX Performance and Coverage Analyzer (PCA) and the VAX System Performance Monitor (SPM) helped developers optimize code.
Influence and Technical Legacy
Impact on CISC and RISC Design
The VAX’s elaborate instruction set inspired later CISC processors, such as the Motorola 68000 and Intel 80386, but also demonstrated the performance limitations of overly complex instructions. The rise of RISC in the 1980s was partly a reaction against the VAX’s microcoded complexity.
Virtual Memory Concepts
The VAX’s paged virtual memory with separate system and user spaces influenced the design of operating systems like Unix and Windows NT. The concept of a 4 GB flat address space became standard for 32-bit architectures.
Emulation and Modern Preservation Efforts
Several VAX emulators, such as SIMH, CHARON-VAX, and E11, allow legacy VMS and Ultrix software to run on modern hardware. Enthusiasts and organizations continue to use emulated VAX systems to preserve historical software and data. The OpenVMS operating system still exists (now maintained by VMS Software Inc.) and runs on HP Integrity and x86-64 systems, but the native VAX architecture is solely of historical interest.