DEC PDP-10 - Ciallo Wiki

The DEC PDP‑10 (Programmed Data Processor, model 10) is a mainframe computer family introduced by Digital Equipment Corporation (DEC) in the late 1960s. Originally developed as a time‑sharing system, the PDP‑10 architecture featured a 36‑bit word length, which enabled efficient handling of complex data structures and character processing. The system became widely used in academic, research, and early networking environments, playing a pivotal role in the development of the ARPANET and early internet protocols. Its primary operating systems—TOPS‑10 and later TOPS‑20—provided powerful multi‑user capabilities and influenced subsequent operating system design. The PDP‑10 line was discontinued in the mid‑1980s, but its legacy persists through emulators and enthusiast communities.

1.1 Historical context and market position

In the 1960s, most computing was batch‑oriented, with users submitting jobs on punched cards and waiting hours for results. A few systems, such as the Compatible Time‑Sharing System (CTSS) at MIT, demonstrated the potential of interactive computing. DEC, already successful with the 12‑bit PDP‑8 and 18‑bit PDP‑9, saw an opportunity to create a large machine optimized for time‑sharing. The PDP‑10 was introduced in 1968, competing with the IBM System/360 family and the SDS Sigma 7. Its relatively low cost—compared to other mainframes—made it attractive to universities and research labs. Over its lifetime, about 700 systems were sold, a modest number but highly influential in the nascent computing‑science community.

The PDP‑10 was designed from the outset for interactive, multi‑user operation. Its 36‑bit word length was chosen for several reasons: it allowed two 18‑bit addresses to fit in one word (simplifying instruction encoding), it could hold six 6‑bit characters or five 7‑bit ASCII characters, and it provided a large address space for its era. The architecture supported privileged and user modes, memory protection, and a powerful interrupt system. These features made it ideal for timesharing, where many users simultaneously ran interactive programs from remote terminals.

1.3 Major models and evolution (KA10, KI10, KL10, KS10)

The PDP‑10 family evolved through four major processor implementations, each offering improvements in speed, memory capacity, and reliability.

1.3.1 KA10: first generation (1968)

The KA10 was the original PDP‑10 processor, built from discrete transistors and ferrite‑core memory. It operated at a clock speed of approximately 1 MHz and supported up to 256K words (about 1MB) of memory. The KA10 used a simple two‑address instruction format and included hardware for integer arithmetic, logical operations, and character manipulation. It lacked virtual memory; all addressing was physical. Several KA10 systems were installed at MIT, Stanford, and Carnegie Mellon, where they formed the basis for early ARPANET nodes.

1.3.2 KI10: improved performance and memory management

Introduced in 1972, the KI10 used integrated circuits (TTL logic) for the processor and memory controller. It offered a 20–30% performance increase over the KA10 and introduced a separate memory system with up to 4 million words, aided by a paging mechanism that provided a primitive form of virtual memory. The KI10 also added instructions for byte manipulation and extended addressing. It was often paired with the RH10 massbus controller for disk storage.

1.3.3 KL10: high‑end processor with cache

Released in 1975, the KL10 was the most powerful PDP‑10 model, built from ECL logic for higher speed. It included a 1‑Kword cache (later expandable to 2 Kwords) and a full 22‑bit address space allowing up to 4 million words of physical memory. The KL10 also supported multiprocessing with two CPUs sharing the same memory. It became the platform for TOPS‑20 and was used in DECSYSTEM‑20 configurations. The KL10 remained in production until the late 1980s, with many units still in service at universities and research labs.

1.3.4 KS10: low‑cost version for smaller institutions

Introduced in 1978, the KS10 used high‑density LSI chips (the AMD 2901 bit‑slice processor) to reduce cost and physical footprint. It was fully compatible with the KL10 instruction set but operated at about one‑third the speed. The KS10 supported up to 2 million words of memory and was often sold with a smaller disk drive. It targeted smaller colleges and departments that could not afford a full KL10 system. Approximately 200 KS10s were sold, making it the most numerous PDP‑10 model.

2.1 Processor design: word length, registers, and instruction set

The PDP‑10 architecture is centered on a 36‑bit word. The processor contains 16 general‑purpose registers (R0 through R15), each 36 bits wide. Register R15 is additionally used as the program counter when the processor is in executive mode. The instruction set includes arithmetic (add, subtract, multiply, divide), logical (and, or, xor), shift, and control (branch, jump, subroutine call) operations. Most instructions operate on full words, but byte‑manipulation instructions allow extraction and insertion of arbitrary bit fields.

2.1.1 General registers and addressing modes

The 16 general registers can be used as accumulators for arithmetic or as base registers for indexing. Addressing modes include direct (the address field contains the operand address), indexed (using a register as an index), and indirect (the address field points to a memory word that contains the effective address). A special half‑word operation allows treating a 36‑bit word as two 18‑bit halves, each containing a separate address, enabling efficient list processing.

2.1.2 Instruction formats: arithmetic, logical, and control

Instructions are one word (36 bits) and are divided into an opcode (9 bits) and an address field (27 bits). The address field can specify a register, a memory address, or an immediate operand. Arithmetic instructions such as ADD, SUB, MUL, and DIV operate in two's complement. Logical operations include AND, OR, XOR, and SETZ (set to zero). Control instructions include JUMP, JUMPA (always), conditional jumps (e.g., JUMPE for jump if equal), and the PUSHJ/POPJ pair for subroutine linkage.

2.2 Memory system

2.2.1 Core memory and later semiconductor memory

Early PDP‑10 systems used ferrite‑core memory, with cycle times around 1–2 microseconds. The core memory was organized in 36‑bit words and often installed in cabinets containing 8K or 16K words per board. Later models, especially the KL10 and KS10, adopted semiconductor dynamic RAM, which reduced power consumption and increased capacity. By the 1980s, PDP‑10 systems could have up to 4 million words (16 megabytes) of memory.

2.2.2 Address space and paging

The KA10 addressed physical memory only, with an 18‑bit address space (256K words). The KI10 introduced a paging system that mapped 18‑bit virtual addresses into physical memory using a page table. The page size was 512 words. The KL10 extended the virtual address to 22 bits, providing a 4‑million‑word virtual space, and added a hardware translation lookaside buffer (TLB) for fast address translation. The KS10 used a similar paging scheme but with a smaller TLB.

2.3 Input/output subsystem

2.3.1 Standard peripheral interfaces (DECtape, disk, terminals)

The PDP‑10 could connect to a variety of peripherals. Common mass‑storage devices included DECtape (a continuous‑loop tape cartridge), magnetic tape drives (e.g., TU10), and moving‑head disk drives (e.g., RP04, RP06). Terminals were typically ASCII‑based Teletype Model 33 or DECwriter printers, and later CRT terminals such as the VT05 and VT100. The I/O bus was the UNIBUS (on smaller models) or the more powerful MASSBUS (for high‑speed disk and tape). Each device was assigned a unique channel number, and the processor communicated via programmed I/O or direct memory access.

2.3.2 Direct memory access (DMA) and channel controllers

To offload the CPU, the PDP‑10 used DMA controllers (such as the RH10/RH20 MASSBUS adapters) that could transfer blocks of data between memory and devices without processor intervention. The channel controllers included built‑in error checking and retry logic. Higher‑end systems could have multiple channels running in parallel, enabling concurrent I/O operations. The DMA subsystem was crucial for the time‑sharing workload, as it allowed many users to read/write files without degrading interactive response.

3.1 TOPS‑10 operating system

TOPS‑10 (Timesharing Operating System for the PDP‑10) was the original operating system for the PDP‑10, first released in 1968. It grew out of an earlier monitor called TMS, developed by DEC and Bolt, Beranek, and Newman (BBN). TOPS‑10 was a monolithic, multi‑user time‑sharing system that managed user processes, file storage, and peripheral devices.

3.1.1 Command language and job control

Users interacted with TOPS‑10 through a command language consisting of commands like R (run a program), DIR (list directory), TYPE (display file content), and PIP (peripheral interchange program). The system supported foreground (interactive) and background (batch) jobs. A job control language (JCL) allowed scripts to be submitted for batch processing, using commands like QUEUE and SUBMIT.

3.1.2 File system and device independence

The file system organized files into directories (called "UFDs" for User File Directories) and a master file directory (MFD). Files were named with six‑character names plus a three‑character extension (e.g., PROG.FOR). TOPS‑10 implemented device independence: a user could refer to a logical device name (e.g., DSK for disk, LPT for line printer) and the system would map it to the actual hardware. This allowed programs to work with different peripherals without modification.

TOPS‑10 supported a large number of concurrent users (often 40–60 on a KL10) through efficient scheduling and swapping. The scheduler used a multilevel feedback queue, giving preference to short interactive jobs. The system provided memory protection between users, a priority system, and accounting mechanisms that recorded CPU and I/O usage for billing. It also included a powerful debugger (DDT) and various utilities for file editing, mail, and inter‑user communication.

3.2 TOPS‑20 operating system

TOPS‑20 was a later operating system for the PDP‑10, introduced in 1976. It evolved from the TENEX operating system developed at BBN and was designed to be more user‑friendly and feature‑rich than TOPS‑10.

3.2.1 Evolution from TENEX and TOPS‑10

TENEX (TEN‑EXtended) was developed in the early 1970s at BBN for the PDP‑10, providing a modern virtual‑memory system and an improved command interface. DEC acquired the rights and produced TOPS‑20 as a supported product, while retaining much of TENEX's architecture. TOPS‑20 initially ran exclusively on the KL10 processor and required a paging memory unit.

3.2.2 Virtual memory and process management

TOPS‑20 implemented a full demand‑paged virtual memory system, with pages of 512 words. Each process had a 22‑bit virtual address space, divided into user and executive halves. The memory manager performed page‑in/out automatically, using disk as backing store. Processes were created using a CRE (create process) system call, and inter‑process communication was supported through mailboxes and shared memory.

3.2.3 User interface enhancements

TOPS‑20 introduced a richer command language with command‑line editing, history recall, and online help. Commands included DIRECTORY (listing with wildcards), COPY, RENAME, and EXECUTE. The system also provided a full‑screen editor (TECO) and a file‑transfer utility (FTP). Its user interface was considered ahead of its time and influenced later systems like Unix (particularly the C shell) and VMS.

3.3 Other operating systems and software

3.3.1 ITS (Incompatible Timesharing System)

ITS was developed at the MIT Artificial Intelligence Laboratory in the late 1960s, specifically for the PDP‑10 (starting on a KA10). It was designed to support AI research and featured a highly interactive environment with virtual memory, a device‑independent file system, and powerful debugging tools. ITS was known for its unique user interface—the "DOT" command interpreter—and its support for early network protocols. It was used extensively in the hacker culture at MIT.

3.3.2 Programming languages (FORTRAN, Lisp, Pascal, etc.)

The PDP‑10 ran a wide variety of high‑level languages. FORTRAN IV was standard for scientific computing. The MacLisp dialect (developed at MIT) was widely used for AI and symbolic computation. Pascal was available, as were COBOL, ALGOL, and SNOBOL. The system also provided an assembler (MACRO‑10) and a linker (LINK). The availability of Lisp on the PDP‑10 made it a key platform for early AI research.

3.3.3 Networking software (ARPANET NCP, TCP/IP)

ARPANET software was first developed on the PDP‑10. The Network Control Program (NCP) was the host‑to‑host protocol used before TCP/IP. Several implementations existed, including one for TOPS‑10 and one for ITS. Later, Stanford and BBN ported TCP/IP to the PDP‑10, allowing it to participate in the early Internet. The PDP‑10 also ran FTP, Telnet, and email delivery agents (such as Sendmail precursor delivermail).

4.1 Role in early ARPANET development

The PDP‑10 was the most common host computer on the ARPANET during the 1970s. Its 36‑bit word and powerful operating systems made it ideal for networking research. Many of the original ARPANET nodes were PDP‑10 systems running TOPS‑10 or ITS.

4.1.1 Interfaces and IMP connections

Each ARPANET host connected to an Interface Message Processor (IMP) via a serial line (typically 50 kbps). The PDP‑10 used a special interface, the IMP‑10, which plugged into the UNIBUS or MASSBUS. The interface handled the HDLC framing and checksuming, offloading the CPU from low‑level network tasks. The first IMP (at UCLA) connected to a PDP‑10 running TOPS‑10 at the Network Measurement Center.

4.1.2 Email and file transfer protocols

Early email systems on the PDP‑10 included MAIL (on TOPS‑10) and the ITS mailer (which used the MSG program). The File Transfer Protocol (FTP) was standardized in 1971, with PDP‑10 implementations being among the first. The PDP‑10 also hosted the first networked game, "Spacewar!", accessible across the ARPANET through the "MIT‑DMS" service.

4.2 Influence on later systems and culture

4.2.1 Hacker culture and the PDP‑10 community

The PDP‑10 was central to the development of hacker culture, particularly at MIT, Stanford, and Carnegie Mellon. The "hacker" ethic of free sharing of information and open access to computing resources flourished on ITS and TOPS‑10 systems. Communities like the "Dynamic Modeling Group" (MIT) and the "SAIL" (Stanford AI Lab) used PDP‑10s to create pioneering software, including the first multi‑user dungeons (MUDs) and the "LOGO" programming language.

4.2.2 Legacy in emulation (SIMH, KLH10)

After DEC discontinued the PDP‑10 in 1984, enthusiasts began writing emulators to preserve the software and culture. Bob Supnik's SIMH (2000) includes a PDP‑10 emulator that can run TOPS‑10, TOPS‑20, and ITS. Another emulator, KLH10, is a faithful recreation of the KL10 hardware. These emulators allow modern systems to run original PDP‑10 software, and they are used by hobbyists, museums, and researchers.

4.2.3 Derived architectures (DECSYSTEM‑20)

In the late 1970s, DEC rebranded the PDP‑10 as the DECSYSTEM‑20 (or DEC‑20) to better compete with other mainframes. The DEC‑20 ran TOPS‑20 and was marketed for commercial timesharing and office automation. Despite its technical merits, the DEC‑20 could not match the price/performance of emerging 32‑bit minicomputers like the VAX, and production ended in 1984. Nevertheless, the PDP‑10 architecture influenced later 36‑bit systems, such as the Honeywell 6180 and the GE DATANET‑30, and its design ideas (especially virtual memory and user‑friendly operating systems) can be seen in VAX/VMS and Unix.